SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register clears the TCM Address Parity Errors of R5SS1.
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Instance Name | Physical Address |
---|---|
MSS_CTRL | 50D1 8160h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TCM1_PARITY_CTRL_B1TCM1_ERRADDR_CLR | RESERVED | TCM1_PARITY_CTRL_B1TCM0_ERRADDR_CLR | ||||
NONE | R/W | NONE | R/W | ||||
0h | 0h | 0h | 0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TCM1_PARITY_CTRL_B0CM1_ERRADDR_CLR | RESERVED | TCM1_PARITY_CTRL_B0TCM0_ERRADDR_CLR | ||||
NONE | R/W | NONE | R/W | ||||
0h | 0h | 0h | 0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TCM1_PARITY_CTRL_ATCM1_ERRADDR_CLR | RESERVED | TCM1_PARITY_CTRL_ATCM0_ERRADDR_CLR | ||||
NONE | R/W | NONE | R/W | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:23 | RESERVED | NONE | 0h | Reserved |
22:20 | TCM1_PARITY_CTRL_B1TCM1_ERRADDR_CLR | R/W | 0h | Write pulse bit field: Writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B |
19 | RESERVED | NONE | 0h | Reserved |
18:16 | TCM1_PARITY_CTRL_B1TCM0_ERRADDR_CLR | R/W | 0h | Write pulse bit field: Writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A |
15 | RESERVED | NONE | 0h | Reserved |
14:12 | TCM1_PARITY_CTRL_B0CM1_ERRADDR_CLR | R/W | 0h | Write pulse bit field: Writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B |
11 | RESERVED | NONE | 0h | Reserved |
10:8 | TCM1_PARITY_CTRL_B0TCM0_ERRADDR_CLR | R/W | 0h | Write pulse bit field: Writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A |
7 | RESERVED | NONE | 0h | Reserved |
6:4 | TCM1_PARITY_CTRL_ATCM1_ERRADDR_CLR | R/W | 0h | Write pulse bit field: Writing 3'b111 clears the Address latched after parity error for ATCM of CR5B |
3 | RESERVED | NONE | 0h | Reserved |
2:0 | TCM1_PARITY_CTRL_ATCM0_ERRADDR_CLR | R/W | 0h | Pulse bit-field Writing 3'b111 clears the Address latched after parity error for ATCM of CR5A |