SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register latches the B0TCM Address where the Address Parity Error occurred in R5SS1 CORE0.
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Instance Name | Physical Address |
---|---|
MSS_CTRL | 50D1 816Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ERR_PARITY_B0TCM0_R5SS1_ADDR | ||||||
NONE | R | ||||||
0h | 0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ERR_PARITY_B0TCM0_R5SS1_ADDR | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERR_PARITY_B0TCM0_R5SS1_ADDR | |||||||
R | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:20 | RESERVED | NONE | 0h | Reserved |
19:0 | ERR_PARITY_B0TCM0_R5SS1_ADDR | R | 0h | Address lathched when parity error is occurred for B0TCM of CR5A |