SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.205.1 MSS_CTRL_TPCC_PARITY_CTRL Register (Offset = 18180h) [reset = 0h]

This register Controls the Parity Error detection logic of EDMA TPCC0 Memories.

Table 2-411 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D1 8180h

Figure 2-205 MSS_CTRL_TPCC_PARITY_CTRL Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED							TPCC_PARITY_CTRL_TPCC_A_PARITY_ERR_CLR
NONE							R/W
0h							0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RESERVED			TPCC_PARITY_CTRL_TPCC_A_PARITY_TESTEN	RESERVED			TPCC_PARITY_CTRL_TPCC_A_PARITY_EN
NONE			R/W	NONE			R/W
0h			0h	0h			0h

Table 2-412 MSS_CTRL_TPCC_PARITY_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:17	RESERVED	NONE	0h	Reserved
16	TPCC_PARITY_CTRL_TPCC_A_PARITY_ERR_CLR	R/W	0h	Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr
15:5	RESERVED	NONE	0h	Reserved
4	TPCC_PARITY_CTRL_TPCC_A_PARITY_TESTEN	R/W	0h	parity test enable for tpcc a
3:1	RESERVED	NONE	0h	Reserved
0	TPCC_PARITY_CTRL_TPCC_A_PARITY_EN	R/W	0h	Writing 1'b1 enables parity for TPCC_A