SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.247 MSS_CTRL_MSS_CR5A1_AXI_WR_BUS_SAFETY_FI Register

2.2.247.1 MSS_CTRL_MSS_CR5A1_AXI_WR_BUS_SAFETY_FI Register (Offset = 182E4h) [reset = 0h]

This register is used to Inject fault on the Interconnect Safety comparator of R5SS1 CORE0 AXI WR Initiator Port.

Table 2-495 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D1 82E4h

Figure 2-247 MSS_CTRL_MSS_CR5A1_AXI_WR_BUS_SAFETY_FI Name Register

31	30	29	28	27	26	25	24
MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_SAFE
R/W
0h
23	22	21	20	19	18	17	16
MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_MAIN
R/W
0h
15	14	13	12	11	10	9	8
MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_DATA
R/W
0h
7	6	5	4	3	2	1	0
RESERVED		MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_DED	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_SEC	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_GLOBAL_SAFE_REQ	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_GLOBAL_MAIN_REQ	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_GLOBAL_SAFE	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_GLOBAL_MAIN
NONE		R/W	R/W	R/W	R/W	R/W	R/W
0h		0h	0h	0h	0h	0h	0h

Table 2-496 MSS_CTRL_MSS_CR5A1_AXI_WR_BUS_SAFETY_FI Register Field Descriptions

Bit	Field	Type	Reset	Description
31:24	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_SAFE	R/W	0h	This bitfield is used to inject fault on Read, write, command and request bus on the safe Interconnect. Bit 0 - Set this bit to inject fault on the Command bus. Bit 1 - Set this bit to inject fault on theWrite bus. Bit 2 - Set this bit to inject fault on the Write Status bus. Bit 3 - Set this bit to inject fault on the Read bus. Bit 7- Set this bit to inject fault on the corresponding request bus.
23:16	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_MAIN	R/W	0h	This bitfield is used to inject fault on Read, write, command and request bus on the main Interconnect. Bit 0 - Set this bit to inject fault on the Command bus. Bit 1 - Set this bit to inject fault on theWrite bus. Bit 2 - Set this bit to inject fault on the Write Status bus. Bit 3 - Set this bit to inject fault on the Read bus. Bit 7- Set this bit to inject fault on the corresponding request bus.
15:8	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_DATA	R/W	0h	Set bit 0 to 1'b1 to inject sec and ded faults on [31:0] bits of data bus. Set bit 1 to 1'b1 to inject sec and ded faults on [64:32] bits of data bus.
7:6	RESERVED	NONE	0h	Reserved
5	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_DED	R/W	0h	Set this bit to 1'b1 inject ded error on data at this port
4	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_SEC	R/W	0h	Set this bit to 1'b1 to inject sec error on data at this port
3	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_GLOBAL_SAFE_REQ	R/W	0h	Set this bit 1'b1 to inject fault for request signals on Safe Interconnect. This is enabled only when the 7th bit of safe bitfield of this register and particular bit coressponding to this port on the safe bitfield of this register is set HIGH
2	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_GLOBAL_MAIN_REQ	R/W	0h	Set this bit to 1'b1 to inject fault for request signals on main Interconnect. This is enabled only when the 7th bit of main bitfield of this register and particular bit coressponding to this port on the main bitfield of this register is set HIGH
1	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_GLOBAL_SAFE	R/W	0h	This is a global safe Fault injection signal. Set this bit to inject fault on all the safety buses of the safe interconnect except req signal. Writing a 1'b1 injects fault on interconnect.
0	MSS_CR5A1_AXI_WR_BUS_SAFETY_FI_GLOBAL_MAIN	R/W	0h	This is a global main Fault injection signal. Set this bit to inject fault on all the buses of the main interconnect except req signal. Writing a 1'b1 injects fault on interconnect.