SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register is used to Control and Configure the Interconnect Safety Behaviour of R5SS1 CORE1 AXI WR Initiator Port.
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Instance Name | Physical Address |
---|---|
MSS_CTRL | 50D1 8300h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MSS_CR5B1_AXI_WR_BUS_SAFETY_CTRL_TYPE | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MSS_CR5B1_AXI_WR_BUS_SAFETY_CTRL_ERR_CLEAR | ||||||
NONE | R/W | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSS_CR5B1_AXI_WR_BUS_SAFETY_CTRL_ENABLE | ||||||
NONE | R/W | ||||||
0h | 7h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | RESERVED | NONE | 0h | Reserved |
23:16 | MSS_CR5B1_AXI_WR_BUS_SAFETY_CTRL_TYPE | R | 0h | This bitfield gives a top level idea of the available bus [cmd,wr,ws,rd] for the particular Target/Initiator and whether it follows the VBUS protocol or not. Bit 0 - 1'b1 indicates the Command bus is implemented to this target/initiator else it is set to 1'b0. Bit 1 - 1'b1 indicates the write bus is implemented to this target/initiator else it is set to 1'b0. Bit 2 - 1'b1 indicates the write status bus is implemented to this target/initiator else it is set to 1'b0. Bit 3 - 1'b1 indicates the read bus is implemented to this target/initiator else it is set to 1'b0. Bit 4 - 1'b0 indicates the port follows the VBUS protocol else it is set to 1'b1. Bits 5-7 are set to 3'b000. |
15:9 | RESERVED | NONE | 0h | Reserved |
8 | MSS_CR5B1_AXI_WR_BUS_SAFETY_CTRL_ERR_CLEAR | R/W | 0h | Set this bit to 1'b1 to clear the error status for this port |
7:3 | RESERVED | NONE | 0h | Reserved |
2:0 | MSS_CR5B1_AXI_WR_BUS_SAFETY_CTRL_ENABLE | R/W | 7h | Set this bit to 3'b111 to enable the safety configuration for this port. Set this bit to 3'b000 to disable the safety configuration for this port. |