SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register Indicates the Error Syndrome of Data errors in Bus Safety Comparator of TPTC00_WR Initiator Port.
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Instance Name | Physical Address |
---|---|
MSS_CTRL | 50D1 83ECh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0_D1 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0_D0 | |||||||
R | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:16 | RESERVED | NONE | 0h | Reserved |
15:8 | MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0_D1 | R | 0h | Read this bitfield for Comparator status for Higher 32 bits [63:32] of data bus at this port. It represent the position of the flipped bit in case of SEC. |
7:0 | MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0_D0 | R | 0h | Read this bitfield for Comparator status for lower 32 bits [31:0] of data bus at this port. It represent the position of the flipped bit in case of SEC. |