SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register controls the delay of Reset assertion to the corresponding R5SS.
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Instance Name | Physical Address |
---|---|
MSS_RCM | 5320 8020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RST2ASSERTDLY0_R5B | |||||||
R/W | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RST2ASSERTDLY0_R5A | |||||||
R/W | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RST2ASSERTDLY0_R5SSB | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RST2ASSERTDLY0_R5SSA | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | RST2ASSERTDLY0_R5B | R/W | 0h | Value decides number of cycles to wait before asserting reset for local reset for CORE1 |
23:16 | RST2ASSERTDLY0_R5A | R/W | 0h | Value decides number of cycles to wait before asserting reset for local reset for CORE0. |
15:8 | RST2ASSERTDLY0_R5SSB | R/W | 0h | Value decides number of cycles to wait before asserting reset for global reset for CORE1 |
7:0 | RST2ASSERTDLY0_R5SSA | R/W | 0h | Value decides number of cycles to wait before asserting reset for global reset for CORE0. |