SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
RGMII 50 CLK Divider Value.
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Instance Name | Physical Address |
---|---|
MSS_RCM | 5320 8294h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MSS_MII10_CLK_DIV_VAL_CLKDIVR | |||||||
R/W | |||||||
636363h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MSS_MII10_CLK_DIV_VAL_CLKDIVR | |||||||
R/W | |||||||
636363h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSS_MII10_CLK_DIV_VAL_CLKDIVR | |||||||
R/W | |||||||
636363h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | RESERVED | NONE | 0h | Reserved |
23:0 | MSS_MII10_CLK_DIV_VAL_CLKDIVR | R/W | 636363h | Divider value MII10 selected clock.To set the divider value of [n+1] configure the register to value of '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x15' is required then '0x151515' should be configured to the register. |