SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
XTAL 32K CLK Divider Value for MMC.
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Instance Name | Physical Address |
---|---|
MSS_RCM | 5320 829Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | XTAL_TEMPSENSE_32K_CLK_DIV_VAL_CLKDIVR | ||||||
NONE | R/W | ||||||
0h | 30CC330Ch | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
XTAL_TEMPSENSE_32K_CLK_DIV_VAL_CLKDIVR | |||||||
R/W | |||||||
30CC330Ch | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
XTAL_TEMPSENSE_32K_CLK_DIV_VAL_CLKDIVR | |||||||
R/W | |||||||
30CC330Ch | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XTAL_TEMPSENSE_32K_CLK_DIV_VAL_CLKDIVR | |||||||
R/W | |||||||
30CC330Ch |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:30 | RESERVED | NONE | 0h | Reserved |
29:0 | XTAL_TEMPSENSE_32K_CLK_DIV_VAL_CLKDIVR | R/W | 30CC330Ch | Divider value for XTAL_32K clock. To set the divider value of [n+1] configure the register to value of '0xnnn'. Data should be loaded as multibit. For example: if divider value of '0x30C' is required then register should be configured as follows - bits[9:0] = 0x30C bits[19:10] = 0x30C bits[29:20] = 0x30C This configures the register to 0x30CC330C |