SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register is used to Reset respective IP.
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Instance Name | Physical Address |
---|---|
MSS_RCM | 5320 85D8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MSS_EDMA_RST_CTRL_TPTCA1_ASSERT | RESERVED | MSS_EDMA_RST_CTRL_TPTCA0_ASSERT | ||||
NONE | R/W | NONE | R/W | ||||
0h | 0h | 0h | 0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSS_EDMA_RST_CTRL_TPCCA_ASSERT | RESERVED | MSS_EDMA_RST_CTRL_ASSERT | ||||
NONE | R/W | NONE | R/W | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:15 | RESERVED | NONE | 0h | Reserved |
14:12 | MSS_EDMA_RST_CTRL_TPTCA1_ASSERT | R/W | 0h | This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_TPTCA1 |
11 | RESERVED | NONE | 0h | Reserved |
10:8 | MSS_EDMA_RST_CTRL_TPTCA0_ASSERT | R/W | 0h | This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_TPTCA0 |
7 | RESERVED | NONE | 0h | Reserved |
6:4 | MSS_EDMA_RST_CTRL_TPCCA_ASSERT | R/W | 0h | This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset MSS_TPCCA |
3 | RESERVED | NONE | 0h | Reserved |
2:0 | MSS_EDMA_RST_CTRL_ASSERT | R/W | 0h | This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing 3'b111 will reset EDMA |