SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Warm Reset Config options.
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Instance Name | Physical Address |
---|---|
MSS_TOPRCM | 5320 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | WARM_RESET_CONFIG_WDOG3_RST_EN | RESERVED | WARM_RESET_CONFIG_WDOG2_RST_EN | ||||
NONE | R/W | NONE | R/W | ||||
0h | 7h | 0h | 7h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | WARM_RESET_CONFIG_WDOG1_RST_EN | RESERVED | WARM_RESET_CONFIG_WDOG0_RST_EN | ||||
NONE | R/W | NONE | R/W | ||||
0h | 7h | 0h | 7h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WARM_RESET_CONFIG_TSENSE1_RST_EN | RESERVED | WARM_RESET_CONFIG_TSENSE0_RST_EN | ||||
NONE | R/W | NONE | R/W | ||||
0h | 7h | 0h | 7h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WARM_RESET_CONFIG_DEBUGSS_RST_EN | RESERVED | WARM_RESET_CONFIG_PAD_BYPASS | ||||
NONE | R/W | NONE | R/W | ||||
0h | 7h | 0h | 7h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | NONE | 0h | Reserved |
30:28 | WARM_RESET_CONFIG_WDOG3_RST_EN | R/W | 7h | Enable/Disable WATCHDOG3 triggering Warm Reset Data should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog control on warmreset Write 3'b111 enable corresponding Watchdog control on warmreset |
27 | RESERVED | NONE | 0h | Reserved |
26:24 | WARM_RESET_CONFIG_WDOG2_RST_EN | R/W | 7h | Enable/Disable WATCHDOG2 triggering Warm Reset Data should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog control on warmreset Write 3'b111 enable corresponding Watchdog control on warmreset |
23 | RESERVED | NONE | 0h | Reserved |
22:20 | WARM_RESET_CONFIG_WDOG1_RST_EN | R/W | 7h | Enable/Disable WATCHDOG1 triggering Warm Reset Data should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog control on warmreset Write 3'b111 enable corresponding Watchdog control on warmreset |
19 | RESERVED | NONE | 0h | Reserved |
18:16 | WARM_RESET_CONFIG_WDOG0_RST_EN | R/W | 7h | Enable/Disable WATCHDOG0 triggering Warm Reset Data should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog control on warmreset Write 3'b111 enable corresponding Watchdog control on warmreset |
15 | RESERVED | NONE | 0h | Reserved |
14:12 | WARM_RESET_CONFIG_TSENSE1_RST_EN | R/W | 7h | Data should be loaded as multibit. Write 3'b000 to disable temperature sensor 1 on Warm reset Write 3'b111 to enable temperature sensor 1l on Warm reset |
11 | RESERVED | NONE | 0h | Reserved |
10:8 | WARM_RESET_CONFIG_TSENSE0_RST_EN | R/W | 7h | Data should be loaded as multibit. Write 3'b000 to disable temperature sensor 0 control on Warm reset Write 3'b111 to enable temperature sensor 0 control on Warm reset |
7 | RESERVED | NONE | 0h | Reserved |
6:4 | WARM_RESET_CONFIG_DEBUGSS_RST_EN | R/W | 7h | Enable/Disable DEBUGSS triggering Warm Reset Data should be loaded as multibit. Write 3'b000 to disable debugger control on Warm Reset Write 3'b111 enable debugger control on Warm Reset |
3 | RESERVED | NONE | 0h | Reserved |
2:0 | WARM_RESET_CONFIG_PAD_BYPASS | R/W | 7h | Bypass the Warm reset from Pad Input Data should be loaded as multibit. Write 3'b000 : Pad Warm Reset pin has control over warm reset Write 3'b111 : Pad warm reset pin has no control on warm reset **Note: This bit will only be reset by PORz. |