SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Sense on Power mode value.
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Instance Name | Physical Address |
---|---|
MSS_TOPRCM | 5320 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SOP_MODE_VALUE_VAL | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SOP_MODE_VALUE_VAL | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SOP_MODE_VALUE_VAL | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SOP_MODE_VALUE_VAL | |||||||
R | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | SOP_MODE_VALUE_VAL | R | 0h | Bootmode (SOP_MODE) values and their corresponding mapping SOP3 SOP2 SOP1 SOP0 Bootmode 0 0 0 0 QSPI Functional Mode[4S] 0 0 0 1 UART Functional Mode 0 0 1 0 QSPI Functional Mode[1S] 0 1 0 0 QSPI Functional Mode[4S] 0 1 0 0 QSPI [4S] - Quad Read UART Fallback Mode 0 1 0 1 QSPI [1S] - Quad Read UART Fallback Mode Any undefined values are reserved for future use. Note: Reset value of MMR is 0, but true SOP pin values will latch immediately after PORz reset is released. CPU reads to the MMR will only reflect the SOP mode values latched at reset. |