SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
programing Output delay: time between internal warm reset source assert to warm reset pad deassert.
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Instance Name | Physical Address |
---|---|
MSS_TOPRCM | 5320 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WARM_RSTTIME1_DELAY | ||||||
NONE | R/W | ||||||
0h | 888h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WARM_RSTTIME1_DELAY | |||||||
R/W | |||||||
888h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:12 | RESERVED | NONE | 0h | Reserved |
11:0 | WARM_RSTTIME1_DELAY | R/W | 888h | Program sufficient delay using this bitfield to keep the WARMRSTn pad active for any external devices relying on the reset signal. Refer to Reset Details Section in TRM for more details. Data should be loaded as multibit. For example: if value of 0x5 should be selected then 0x555 should be configured to the register. **Note: This bit will only be reset by PORz. |