SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
programing input Rise delay : time between warm reset pad deassert to chip warm reset deassert.
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Instance Name | Physical Address |
---|---|
MSS_TOPRCM | 5320 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WARM_RSTTIME2_DELAY | ||||||
NONE | R/W | ||||||
0h | 888h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WARM_RSTTIME2_DELAY | |||||||
R/W | |||||||
888h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:12 | RESERVED | NONE | 0h | Reserved |
11:0 | WARM_RSTTIME2_DELAY | R/W | 888h | Program the deassertion delay with this bitfield to control internal system reset deassertion which is relative to the deassertion of WARMRSTn pad. Data should be loaded as multibit. For example: if value of 0x5 should be selected then 0x555 should be configured to the register. **Note: This bit will only be reset by PORz. |