SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
programing Input Fall delay : time between warm reset pad assert to chip warm reset assert.
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Instance Name | Physical Address |
---|---|
MSS_TOPRCM | 5320 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WARM_RSTTIME3_DELAY | ||||||
NONE | R/W | ||||||
0h | 111h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WARM_RSTTIME3_DELAY | |||||||
R/W | |||||||
111h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:12 | RESERVED | NONE | 0h | Reserved |
11:0 | WARM_RSTTIME3_DELAY | R/W | 111h | The glitch filter logic will filter any input pad signal which is LOW for any time less than the delay programmed with this bit.This parameter also programmes the delay from external Warmrestn assertion to Internal system warm resetn assertion. Data should be loaded as multibit. For example: if value of 0x5 should be selected then 0x555 should be configured to the register. **Note: This bit will only be reset by PORz. |