SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.2.25.1 MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT1 Register (Offset = 430h) [reset = 3h]

Core PLL high speed divider clock 1 control.

Table 2-1456 Instance Table

Instance Name	Physical Address
MSS_TOPRCM	5320 0430h

Figure 2-726 MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT1 Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED			PLL_CORE_HSDIVIDER_CLKOUT1_PWDN	RESERVED		PLL_CORE_HSDIVIDER_CLKOUT1_STATUS	PLL_CORE_HSDIVIDER_CLKOUT1_GATE_CTRL
NONE			R/W	NONE		R	R/W
0h			0h	0h		0h	0h
7	6	5	4	3	2	1	0
RESERVED		PLL_CORE_HSDIVIDER_CLKOUT1_DIVCHACK	PLL_CORE_HSDIVIDER_CLKOUT1_DIV
NONE		R	R/W
0h		0h	3h

Table 2-1457 MSS_TOPRCM_PLL_CORE_HSDIVIDER_CLKOUT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:13	RESERVED	NONE	0h	Reserved
12	PLL_CORE_HSDIVIDER_CLKOUT1_PWDN	R/W	0h	Power down for HSDIVIDER CLKOUT1 divider and hence CLKOUT1 output 0h[R/W] = CLKOUT1 divider active 1h[R/W] = CLKOUT1 divider is powered down
11:10	RESERVED	NONE	0h	Reserved
9	PLL_CORE_HSDIVIDER_CLKOUT1_STATUS	R	0h	HSDIVIDER CLKOUT1 status 0h[R] = The clock output is gated 1h[R] = The clock output is enabled
8	PLL_CORE_HSDIVIDER_CLKOUT1_GATE_CTRL	R/W	0h	Control gating of HSDIVIDER CLKOUT1 0h[R/W] = Automatically gate this clock when there is no dependency for it 1h[R/W] = Force this clock to stay enabled even if there is no request
7:6	RESERVED	NONE	0h	Reserved
5	PLL_CORE_HSDIVIDER_CLKOUT1_DIVCHACK	R	0h	Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect
4:0	PLL_CORE_HSDIVIDER_CLKOUT1_DIV	R/W	3h	DPLL post-divider factor, HSDIVIDER CLKOUT1, for internal clock generation. Divide values from 1 to 31. 0h[R/W] = Reserved