SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Clock Divider register for System Clock.
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Instance Name | Physical Address |
---|---|
MSS_TOPRCM | 5320 0520h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SYS_CLK_DIV_VAL_CLKDIV | ||||||
NONE | R/W | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYS_CLK_DIV_VAL_CLKDIV | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:12 | RESERVED | NONE | 0h | Reserved |
11:0 | SYS_CLK_DIV_VAL_CLKDIV | R/W | 0h | Divider value for System Clock selected clock..To set the divider value of [n+1] configure the register to '0xnnn'.Data should be loaded as multibit. For example: if divider value of '0x9' is required then '0x888' should be configured to the register. |