SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.5.2.39 MSS_TOPRCM_PLL_PER_CLKCTRL Register

5.2.39.1 MSS_TOPRCM_PLL_PER_CLKCTRL Register (Offset = 804h) [reset = 895000h]

Clock control for Peripheral PLL.

Table 2-1484 Instance Table

Instance Name	Physical Address
MSS_TOPRCM	5320 0804h

Figure 2-740 MSS_TOPRCM_PLL_PER_CLKCTRL Name Register

31	30	29	28	27	26	25	24
PLL_PER_CLKCTRL_CYCLESLIPEN	PLL_PER_CLKCTRL_ENSSC	PLL_PER_CLKCTRL_CLKDCOLDOEN	RESERVED
R/W	R/W	R/W	NONE
0h	0h	0h	0h
23	22	21	20	19	18	17	16
PLL_PER_CLKCTRL_IDLE	PLL_PER_CLKCTRL_BYPASSACKZ	PLL_PER_CLKCTRL_STBYRET	PLL_PER_CLKCTRL_CLKOUTEN	PLL_PER_CLKCTRL_CLKOUTLDOEN	PLL_PER_CLKCTRL_ULOWCLKEN	PLL_PER_CLKCTRL_CLKDCOLDOPWDNZ	PLL_PER_CLKCTRL_M2PWDNZ
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
1h	0h	0h	0h	1h	0h	0h	1h
15	14	13	12	11	10	9	8
RESERVED	PLL_PER_CLKCTRL_STOPMODE	RESERVED	PLL_PER_CLKCTRL_SELFREQDCO			RESERVED	PLL_PER_CLKCTRL_RELAXED_LOCK
NONE	R/W	NONE	R/W			NONE	R/W
0h	1h	0h	4h			0h	0h
7	6	5	4	3	2	1	0
RESERVED						PLL_PER_CLKCTRL_SSCTYPE	PLL_PER_CLKCTRL_TINTZ
NONE						R/W	R/W
0h						0h	0h

Table 2-1485 MSS_TOPRCM_PLL_PER_CLKCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PLL_PER_CLKCTRL_CYCLESLIPEN	R/W	0h	FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK. Cycleslip could be caused if loop is not able to track input clock. Default = 1'b0 recommended
30	PLL_PER_CLKCTRL_ENSSC	R/W	0h	Controls Clock SpReading. SSC is not supported. Should be set to 0x0 to disable clock spReading.
29	PLL_PER_CLKCTRL_CLKDCOLDOEN	R/W	0h	Synchronously enables/disables CLKDCOLDO 0x0 : synchronously disables CLKDCOLDO 0x1 : synchronously enables CLKDCOLDO
28:24	RESERVED	NONE	0h	Reserved
23	PLL_PER_CLKCTRL_IDLE	R/W	1h	Sets PLL to Idle mode 0x0 : When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL will go to Active and Locked 0x1 : When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL will go to Idle Bypass low powe
22	PLL_PER_CLKCTRL_BYPASSACKZ	R/W	0h	BYPASSACKZ is a special purpose input to the module. In general this input is expected to be tied to static low. For the output clocks of the module that do not have an internal bypass mux viz. CLKDCOLDO and CLKOUTLDO, a bypass mux could be implemented external to the module.
21	PLL_PER_CLKCTRL_STBYRET	R/W	0h	Standby retention control 0x0 : prepares ADPLLLJ for relock when out of retention by removing the gating on all internal clocks. 0x1 : prepares ADPLLLJ for retention by gating all the internal clocks.
20	PLL_PER_CLKCTRL_CLKOUTEN	R/W	0h	CLKOUT enable or disable 0x0 : synchronously disables CLKOUT 0x1 : synchronously enables CLKOUT
19	PLL_PER_CLKCTRL_CLKOUTLDOEN	R/W	1h	Synchronously enables/disables CLKOUTLDO 0x0 : synchronously disables CLKOUTLDO 0x1 : synchronously enables CLKOUTLDO
18	PLL_PER_CLKCTRL_ULOWCLKEN	R/W	0h	Select CLKOUT source in bypass 0x0: When ADPLLLJ in bypass mode, CLKOUT = CLKINP/[N2+1] 0x1: When ADPLLLJ in bypass mode, CLKOUT = CLKINPULOW.
17	PLL_PER_CLKCTRL_CLKDCOLDOPWDNZ	R/W	0h	0 Asynchronous power down for CLKDCOLDO o/p.
16	PLL_PER_CLKCTRL_M2PWDNZ	R/W	1h	M2 divider power down mode 0x0: Asynchronous power down for M2 divider 0x1 : M2 divider is functional
15	RESERVED	NONE	0h	Reserved
14	PLL_PER_CLKCTRL_STOPMODE	R/W	1h	When in Lossclk/Stbyret 0x0 : Limp mode 0x1 : Stopmode
13	RESERVED	NONE	0h	Reserved
12:10	PLL_PER_CLKCTRL_SELFREQDCO	R/W	4h	DCO Clock [DCOCLK = CLKINP * [M/[N+1]]] frequency range selector. 0x0: Reserved 0x2: HS2 : DCOCLK range is from 500 MHz to 1000MHz 0x3: Reserved 0x4: HS1: DCOCLK range is from 1000MHz to 2000MHz 0x5: Reserved
9	RESERVED	NONE	0h	Reserved
8	PLL_PER_CLKCTRL_RELAXED_LOCK	R/W	0h	Decides when FREQLOCK asserted 0x0: FREQLOCK asserted when DC frequency error less than 1% 0x1: FREQLOCK asserted when DC frequency error less than 2%
7:2	RESERVED	NONE	0h	Reserved
1	PLL_PER_CLKCTRL_SSCTYPE	R/W	0h	SSC Type - This should be configured as 1'b0. The module does not support spread spectrum clocking [SSC] on its output clocks.
0	PLL_PER_CLKCTRL_TINTZ	R/W	0h	PLL core soft reset. TINITZ activation [Low] gives softreset to ADPLLLJ. TINITZ does not reset the entire digital control logic; it forces the FSM into RESET State so that ADPLLLJ could restart.