SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Fractionsl divider and Sigma Delta config register for peripheral PLL.
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Instance Name | Physical Address |
---|---|
MSS_TOPRCM | 5320 0818h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PLL_PER_FRACDIV_REGSD | |||||||
R/W | |||||||
8h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PLL_PER_FRACDIV_FRACTIONALM | ||||||
NONE | R/W | ||||||
0h | 0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PLL_PER_FRACDIV_FRACTIONALM | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL_PER_FRACDIV_FRACTIONALM | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | PLL_PER_FRACDIV_REGSD | R/W | 8h | Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance. DPLL_SD_DIV = CEILING [[DPLL_MULT/[DPLL_DIV+1]] * CLKINP/ 250], where CLKINP is the input clock of the DPLL in MHz |
23:18 | RESERVED | NONE | 0h | Reserved |
17:0 | PLL_PER_FRACDIV_FRACTIONALM | R/W | 0h | Fractional part of the M divider.The 18bit FractionalM value is loaded into DPLL on the rising edge of TENABLE signal .To enable Integer only division FractionalM should be set to 18'b0. |