SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register provides details on EFUSE values written into Row 12.
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Instance Name | Physical Address |
---|---|
TOP_CTRL | 50D8 0428h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EFUSE1_ROW_12_CUSTOMER_IP_DISABLE | EFUSE1_ROW_12_EPWM_FEATURE_DISABLE | |||||
NONE | R | R | |||||
0h | 0h | 0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EFUSE1_ROW_12_CANFD_DIS | EFUSE1_ROW_12_PRU-ICSS_HW_DIS | ||||||
R | R | ||||||
0h | 0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EFUSE1_ROW_12_PRU-ICSS_HW_DIS | EFUSE1_ROW_12_PRU-ICSS_DIS | EFUSE1_ROW_12_TWOX_CTRL_PERIP_DISABLE | EFUSE1_ROW_12_R5SS_FREQ | EFUSE1_ROW_12_R5SS1_DISABLE | |||
R | R | R | R | R | |||
0h | 0h | 0h | 0h | 0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EFUSE1_ROW_12_R5SS1_DUAL_CORE_DISABLE | EFUSE1_ROW_12_R5SS1_FORCE_DUAL_CORE | EFUSE1_ROW_12_R5SS0_DUAL_CORE_DISABLE | EFUSE1_ROW_12_R5SS0_FORCE_DUAL_CORE | EFUSE1_ROW_12_L2_MEM_SIZE | |||
R | R | R | R | R | |||
0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:26 | RESERVED | NONE | 0h | Reserved |
25 | EFUSE1_ROW_12_CUSTOMER_IP_DISABLE | R | 0h | Customer IP set control 0 - All IPs enabled 1 - Customer IP set disabled [PWM24-31,CMPSSA6-9,CMPSSB6-9 disabled] |
24 | EFUSE1_ROW_12_EPWM_FEATURE_DISABLE | R | 0h | Customer protected features inside PWM IP 0 - All features enabled 1 - Customer defined features are protected |
23:20 | EFUSE1_ROW_12_CANFD_DIS | R | 0h | CANFD disables. Bit positions correspond to CAN instance. 0 - CAN is enabled 1 - CAN is disabled |
19:12 | EFUSE1_ROW_12_PRU-ICSS_HW_DIS | R | 0h | ICSSM IP feature configuration 0 - ICSSM feature enabled 1 - ICSSM feature disabled |
11 | EFUSE1_ROW_12_PRU-ICSS_DIS | R | 0h | ICSSM IP disable 0 - ICSSM enabled 1 - ICSSM disabled |
10 | EFUSE1_ROW_12_TWOX_CTRL_PERIP_DISABLE | R | 0h | 2x control IPs enabled 0 - 1x control IPs |
9 | EFUSE1_ROW_12_R5SS_FREQ | R | 0h | R5SS Freq 0 - 400 MHz 1 - 200 MHz |
8 | EFUSE1_ROW_12_R5SS1_DISABLE | R | 0h | Supports single R5SS0 cluster, disables R5SS1 cluster |
7 | EFUSE1_ROW_12_R5SS1_DUAL_CORE_DISABLE | R | 0h | Disabling switching to Dual Core mode by the application. Forced lockstep is forced dual core not enabled |
6 | EFUSE1_ROW_12_R5SS1_FORCE_DUAL_CORE | R | 0h | Enable MSS R5FSS1 dual core boot mode. Force Dual core |
5 | EFUSE1_ROW_12_R5SS0_DUAL_CORE_DISABLE | R | 0h | Disabling switching to Dual Core mode by the application. Forced lockstep is forced dual core not enabled |
4 | EFUSE1_ROW_12_R5SS0_FORCE_DUAL_CORE | R | 0h | Enable MSS R5FSS0 dual core boot mode. Force Dual core |
3:0 | EFUSE1_ROW_12_L2_MEM_SIZE | R | 0h | Decides memory size 0000- L2- 2 MB 0001- L2- 1.5 MB 0010- L2- 1 MB 0011- L2- 0.5 MB Others - Reserved |