SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.23.1 TOP_CTRL_MASK_VMON_ERROR_ESM_L Register (Offset = C24h) [reset = 1FFFFh]

This register is used to select the voltage monitors whose Error staus should triggering the ESM Low Interrupt.

Table 2-974 Instance Table

Instance Name	Physical Address
TOP_CTRL	50D8 0C24h

Figure 2-486 TOP_CTRL_MASK_VMON_ERROR_ESM_L Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED							MASK_VMON_ERROR_ESM_L_ADC34_REF_UV_MASK
NONE							R/W
0h							1h
15	14	13	12	11	10	9	8
MASK_VMON_ERROR_ESM_L_ADC34_REF_OV_MASK	MASK_VMON_ERROR_ESM_L_ADC12_REF_UV_MASK	MASK_VMON_ERROR_ESM_L_ADC12_REF_OV_MASK	MASK_VMON_ERROR_ESM_L_ADC0_REF_UV_MASK	MASK_VMON_ERROR_ESM_L_ADC0_REF_OV_MASK	MASK_VMON_ERROR_ESM_L_CMP8_UV_ERR_MASK	MASK_VMON_ERROR_ESM_L_CMP7_UV_ERR_MASK	MASK_VMON_ERROR_ESM_L_CMP5_UV_ERR_MASK
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
1h	1h	1h	1h	1h	1h	1h	1h
7	6	5	4	3	2	1	0
MASK_VMON_ERROR_ESM_L_CMP5_OV_ERR_MASK	MASK_VMON_ERROR_ESM_L_CMP3_UV_ERR_MASK	MASK_VMON_ERROR_ESM_L_CMP3_OV_ERR_MASK	MASK_VMON_ERROR_ESM_L_CMP2_UV_ERR_MASK	MASK_VMON_ERROR_ESM_L_CMP2_OV_ERR_MASK	MASK_VMON_ERROR_ESM_L_CMP1_UV_ERR_NASK	MASK_VMON_ERROR_ESM_L_CMP1_OV_ERR_MASK	MASK_VMON_ERROR_ESM_L_CMP0_UV_ERR_MASK
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
1h	1h	1h	1h	1h	1h	1h	1h

Table 2-975 TOP_CTRL_MASK_VMON_ERROR_ESM_L Register Field Descriptions

Bit	Field	Type	Reset	Description
31:17	RESERVED	NONE	0h	Reserved
16	MASK_VMON_ERROR_ESM_L_ADC34_REF_UV_MASK	R/W	1h	VMON Error Mask to INTR
15	MASK_VMON_ERROR_ESM_L_ADC34_REF_OV_MASK	R/W	1h	VMON Error Mask to INTR
14	MASK_VMON_ERROR_ESM_L_ADC12_REF_UV_MASK	R/W	1h	VMON Error Mask to INTR
13	MASK_VMON_ERROR_ESM_L_ADC12_REF_OV_MASK	R/W	1h	VMON Error Mask to INTR
12	MASK_VMON_ERROR_ESM_L_ADC0_REF_UV_MASK	R/W	1h	VMON Error Mask to INTR
11	MASK_VMON_ERROR_ESM_L_ADC0_REF_OV_MASK	R/W	1h	VMON Error Mask to INTR
10	MASK_VMON_ERROR_ESM_L_CMP8_UV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
9	MASK_VMON_ERROR_ESM_L_CMP7_UV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
8	MASK_VMON_ERROR_ESM_L_CMP5_UV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
7	MASK_VMON_ERROR_ESM_L_CMP5_OV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
6	MASK_VMON_ERROR_ESM_L_CMP3_UV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
5	MASK_VMON_ERROR_ESM_L_CMP3_OV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
4	MASK_VMON_ERROR_ESM_L_CMP2_UV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
3	MASK_VMON_ERROR_ESM_L_CMP2_OV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
2	MASK_VMON_ERROR_ESM_L_CMP1_UV_ERR_NASK	R/W	1h	VMON Error Mask to INTR
1	MASK_VMON_ERROR_ESM_L_CMP1_OV_ERR_MASK	R/W	1h	VMON Error Mask to INTR
0	MASK_VMON_ERROR_ESM_L_CMP0_UV_ERR_MASK	R/W	1h	VMON Error Mask to INTR