SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Config Error Enable and Clear Register.
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Instance Name | Physical Address |
---|---|
ESM0 | 52D0 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSK | ||||||
NONE | R/W1TC | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:3 | RESERVED | NONE | 0h | Reserved |
2:0 | MSK | R/W1TC | 0h | This is the masked status for errors in the configuration for Group N. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. Read: 1'b0:Inactive 1'b1:Active/Pending and Enabled Write 1'b1 to clear event raw status. Bits associated with groups that are not implemented in a certain configuration are Reserved, Read as 0 and writes will have no effect |