SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register controls the error_pin_n output.
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Instance Name | Physical Address |
---|---|
ESM0 | 52D0 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWM_EN | KEY | ||||||
R/W | R/W | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:8 | RESERVED | NONE | 0h | Reserved |
7:4 | PWM_EN | R/W | 0h | PWM mode enable. This field should only be modified when the ESM is disabled, from the Global Enable register. This field is only reset by a Power-On-Reset (not warm reset). 4'b0000:Error output pin is a level 4'b1111:Error output pin is a PWM signal All other are invalid |
3:0 | KEY | R/W | 0h | This field controls behavior of the Error Pin. Note, during reset the field is 4'b0000, but the Error Pin is asserted (active low). Immediately after reset, the Error Pin de-asserts. This field is only reset by a Power-On-Reset (not warm reset). 4'b0000 : Normal Mode - Error Pin will activate when an enabled Error Event occurs 4'b1010 : Force Error Mode - Forces the Error Pin active. To clear the Error Pin (return to the ESM_IDLE state) write this field back to Normal Mode (Writing a CLEAR event will also work). You may only write to Force Error Mode while in IDLE. Attempting Force Error while in another state will have no effect 4'b0101 : CLEAR Event - generates a CLEAR event to the ESM state machine. key will return to Normal Mode (4'b0000) on the next cycle. All Other Values - Normal Mode. Writing any of these values will have no effect. Reading any of these values indicate that one or more bits have experienced a single event upset and software should write the field back to 4'b0000. The ESM will continue to operate in Normal Mode |