SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Level Error Enable Set Register
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Offset = Base + (j * 20h); where j = 0 to 2d
Instance Name | Physical Address |
---|---|
ESM0 | 52D0 0408h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MSK | |||||||
R/W1TS | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MSK | |||||||
R/W1TS | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MSK | |||||||
R/W1TS | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||
R/W1TS | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | MSK | R/W1TS | 0h | This field is used to enable the mask of events in group N. Each bit corresponds to event Q where Q = N*32+Bit. If the corresponding bit and the global_enable are set, then then interrupt is unmasked. This field is only reset by a Power-On-Reset (not warm reset). A global soft reset will set this field to 0. Read: 1'b0: Disabled 1'b1: Enabled Write 1'b1 to set enable |