SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.19.1 ADC_RESULTS_ADCPPB3RESULT Register (Offset = 28h) [reset = 0h]

ADC Post Processing Block 3 Result Register.

Table 3-41 Instance Table

Figure 3-19 ADC_RESULTS_ADCPPB3RESULT Name Register

Table 3-42 ADC_RESULTS_ADCPPB3RESULT Register Field Descriptions

Bit	Field	Type	Reset	Description
31:16	SIGN	R	0h	Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the SIGN bits extend down to bit 12, and all reflect the same value as bit 12.
15:0	PPBRESULT	R	0h	ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. This result is available 1 SYSCLK cycle after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 1 SYSCLK cycle after the associated ADCRESULT and subsequent results [in order from lowest numbered PPB to highest] will each become available every 2-3 SYSCLK cycles [refer to the TRM for more detailed timing information]. If ADCINTFLG is polled to determine when to read the PPBRESULT, it may be necessary to add one or more NOP instructions to ensure that the updated post conversion processing result has posted to the register. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion, the PPBRESULT bits are limited to bits 12:0.