SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
ADC PPB 4 Final Sum Result Register.
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Instance Name | Physical Address |
---|---|
ADC0_G0_G5 | 5010 0048h |
ADC1_G0_G5 | 5010 1048h |
ADC2_G0_G5 | 5010 2048h |
ADC3_G0_G5 | 5010 3048h |
ADC4_G0_G5 | 5010 4048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SIGN | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SUM | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SUM | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SUM | |||||||
R | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | SIGN | R | 0h | Sign Extended Bits. These bits reflect the same value as bit 23. |
23:0 | SUM | R | 0h | Post Processing Block 4 Oversampling Final Sum. When either a count-match event occurs [PCOUNT = LIMIT] or PPB4 receives a sync. event, the value of PSUM is loaded into this register. In the case of a count-match event, the sum loaded into this register includes the value from the most recent conversion. The value from PSUM will be right shifted by the amount specified in the SHIFT register before being loaded into the final SUM result register. This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available [only in case of a count-match event]. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC [refer to the ADCPPB4RESULT timing information]. |