SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
CC Error Register
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Instance Name | Physical Address |
---|---|
EDMA0 | 52A0 0318h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RES33 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RES33 | TCERR | ||||||
R | R | ||||||
0h | 0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RES34 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QTHRXCD7 | QTHRXCD6 | QTHRXCD5 | QTHRXCD4 | QTHRXCD3 | QTHRXCD2 | QTHRXCD1 | QTHRXCD0 |
R | R | R | R | R | R | R | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:17 | RES33 | R | 0h | RESERVE FIELD |
16 | TCERR | R | 0h | Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors were previously clear] then an error will be signaled with TPCC error interrupt. |
15:8 | RES34 | R | 0h | RESERVE FIELD |
7 | QTHRXCD7 | R | 0h | Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors [including EMR/QEMR] were previously clear] then an error will be signaled with the TPCC error interrupt. |
6 | QTHRXCD6 | R | 0h | Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors [including EMR/QEMR] were previously clear] then an error will be signaled with the TPCC error interrupt. |
5 | QTHRXCD5 | R | 0h | Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors [including EMR/QEMR] were previously clear] then an error will be signaled with the TPCC error interrupt. |
4 | QTHRXCD4 | R | 0h | Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors [including EMR/QEMR] were previously clear] then an error will be signaled with the TPCC error interrupt. |
3 | QTHRXCD3 | R | 0h | Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors [including EMR/QEMR] were previously clear] then an error will be signaled with the TPCC error interrupt. |
2 | QTHRXCD2 | R | 0h | Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors [including EMR/QEMR] were previously clear] then an error will be signaled with the TPCC error interrupt. |
1 | QTHRXCD1 | R | 0h | Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors [including EMR/QEMR] were previously clear] then an error will be signaled with the TPCC error interrupt. |
0 | QTHRXCD0 | R | 0h | Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by Writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set [and all errors [including EMR/QEMR] were previously clear] then an error will be signaled with the TPCC error interrupt. |