SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.4.2.44 TPCC_ERH Register

4.2.44.1 TPCC_ERH Register (Offset = 1004h) [reset = 0h]

Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register.

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Table 4-1478 Instance Table

Instance Name	Physical Address
EDMA0	52A0 1004h

Figure 4-721 TPCC_ERH Name Register

31	30	29	28	27	26	25	24
E63	E62	E61	E60	E59	E58	E57	E56
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
E55	E54	E53	E52	E51	E50	E49	E48
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
E47	E46	E45	E44	E43	E42	E41	E40
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
E39	E38	E37	E36	E35	E34	E33	E32
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h

Table 4-1479 TPCC_ERH Register Field Descriptions

Bit	Field	Type	Reset	Description
31	E63	R	0h	Event #63
30	E62	R	0h	Event #62
29	E61	R	0h	Event #61
28	E60	R	0h	Event #60
27	E59	R	0h	Event #59
26	E58	R	0h	Event #58
25	E57	R	0h	Event #57
24	E56	R	0h	Event #56
23	E55	R	0h	Event #55
22	E54	R	0h	Event #54
21	E53	R	0h	Event #53
20	E52	R	0h	Event #52
19	E51	R	0h	Event #51
18	E50	R	0h	Event #50
17	E49	R	0h	Event #49
16	E48	R	0h	Event #48
15	E47	R	0h	Event #47
14	E46	R	0h	Event #46
13	E45	R	0h	Event #45
12	E44	R	0h	Event #44
11	E43	R	0h	Event #43
10	E42	R	0h	Event #42
9	E41	R	0h	Event #41
8	E40	R	0h	Event #40
7	E39	R	0h	Event #39
6	E38	R	0h	Event #38
5	E37	R	0h	Event #37
4	E36	R	0h	Event #36
3	E35	R	0h	Event #35
2	E34	R	0h	Event #34
1	E33	R	0h	Event #33
0	E32	R	0h	Event #32

31	30	29	28	27	26	25	24
E63	E62	E61	E60	E59	E58	E57	E56
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
E55	E54	E53	E52	E51	E50	E49	E48
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
E47	E46	E45	E44	E43	E42	E41	E40
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
E39	E38	E37	E36	E35	E34	E33	E32
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h

31	30	29	28	27	26	25	24
E63	E62	E61	E60	E59	E58	E57	E56
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
E55	E54	E53	E52	E51	E50	E49	E48
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
E47	E46	E45	E44	E43	E42	E41	E40
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
E39	E38	E37	E36	E35	E34	E33	E32
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h

31	30	29	28	27	26	25	24
E63	E62	E61	E60	E59	E58	E57	E56
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
E55	E54	E53	E52	E51	E50	E49	E48
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
E47	E46	E45	E44	E43	E42	E41	E40
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
E39	E38	E37	E36	E35	E34	E33	E32
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h