SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.4.2.72 TPCC_QER Register

4.2.72.1 TPCC_QER Register (Offset = 1080h) [reset = 0h]

QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set.

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Table 4-1534 Instance Table

Instance Name	Physical Address
EDMA0	52A0 1080h

Figure 4-749 TPCC_QER Name Register

31	30	29	28	27	26	25	24
RES70
R
0h
23	22	21	20	19	18	17	16
RES70
R
0h
15	14	13	12	11	10	9	8
RES70
R
0h
7	6	5	4	3	2	1	0
E7	E6	E5	E4	E3	E2	E1	E0
R	R	R	R	R	R	R	R
0h	0h	0h	0h	0h	0h	0h	0h

Table 4-1535 TPCC_QER Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RES70	R	0h	RESERVE FIELD
7	E7	R	0h	Event #7
6	E6	R	0h	Event #6
5	E5	R	0h	Event #5
4	E4	R	0h	Event #4
3	E3	R	0h	Event #3
2	E2	R	0h	Event #2
1	E1	R	0h	Event #1
0	E0	R	0h	Event #0