SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect..
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Instance Name | Physical Address |
---|---|
EDMA0 | 52A0 108Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RES73 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RES73 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RES73 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
E7 | E6 | E5 | E4 | E3 | E2 | E1 | E0 |
W | W | W | W | W | W | W | W |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:8 | RES73 | R | 0h | RESERVE FIELD |
7 | E7 | W | 0h | Event #7 |
6 | E6 | W | 0h | Event #6 |
5 | E5 | W | 0h | Event #5 |
4 | E4 | W | 0h | Event #4 |
3 | E3 | W | 0h | Event #3 |
2 | E2 | W | 0h | Event #2 |
1 | E1 | W | 0h | Event #1 |
0 | E0 | W | 0h | Event #0 |