SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software.
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Instance Name | Physical Address |
---|---|
EDMA0 | 52A0 2018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
E31 | E30 | E29 | E28 | E27 | E26 | E25 | E24 |
R | R | R | R | R | R | R | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
E23 | E22 | E21 | E20 | E19 | E18 | E17 | E16 |
R | R | R | R | R | R | R | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
E15 | E14 | E13 | E12 | E11 | E10 | E9 | E8 |
R | R | R | R | R | R | R | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
E7 | E6 | E5 | E4 | E3 | E2 | E1 | E0 |
R | R | R | R | R | R | R | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | E31 | R | 0h | Event #31 |
30 | E30 | R | 0h | Event #30 |
29 | E29 | R | 0h | Event #29 |
28 | E28 | R | 0h | Event #28 |
27 | E27 | R | 0h | Event #27 |
26 | E26 | R | 0h | Event #26 |
25 | E25 | R | 0h | Event #25 |
24 | E24 | R | 0h | Event #24 |
23 | E23 | R | 0h | Event #23 |
22 | E22 | R | 0h | Event #22 |
21 | E21 | R | 0h | Event #21 |
20 | E20 | R | 0h | Event #20 |
19 | E19 | R | 0h | Event #19 |
18 | E18 | R | 0h | Event #18 |
17 | E17 | R | 0h | Event #17 |
16 | E16 | R | 0h | Event #16 |
15 | E15 | R | 0h | Event #15 |
14 | E14 | R | 0h | Event #14 |
13 | E13 | R | 0h | Event #13 |
12 | E12 | R | 0h | Event #12 |
11 | E11 | R | 0h | Event #11 |
10 | E10 | R | 0h | Event #10 |
9 | E9 | R | 0h | Event #9 |
8 | E8 | R | 0h | Event #8 |
7 | E7 | R | 0h | Event #7 |
6 | E6 | R | 0h | Event #6 |
5 | E5 | R | 0h | Event #5 |
4 | E4 | R | 0h | Event #4 |
3 | E3 | R | 0h | Event #3 |
2 | E2 | R | 0h | Event #2 |
1 | E1 | R | 0h | Event #1 |
0 | E0 | R | 0h | Event #0 |