SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect..
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Instance Name | Physical Address |
---|---|
EDMA0 | 52A0 2030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
E31 | E30 | E29 | E28 | E27 | E26 | E25 | E24 |
W | W | W | W | W | W | W | W |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
E23 | E22 | E21 | E20 | E19 | E18 | E17 | E16 |
W | W | W | W | W | W | W | W |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
E15 | E14 | E13 | E12 | E11 | E10 | E9 | E8 |
W | W | W | W | W | W | W | W |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
E7 | E6 | E5 | E4 | E3 | E2 | E1 | E0 |
W | W | W | W | W | W | W | W |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | E31 | W | 0h | Event #31 |
30 | E30 | W | 0h | Event #30 |
29 | E29 | W | 0h | Event #29 |
28 | E28 | W | 0h | Event #28 |
27 | E27 | W | 0h | Event #27 |
26 | E26 | W | 0h | Event #26 |
25 | E25 | W | 0h | Event #25 |
24 | E24 | W | 0h | Event #24 |
23 | E23 | W | 0h | Event #23 |
22 | E22 | W | 0h | Event #22 |
21 | E21 | W | 0h | Event #21 |
20 | E20 | W | 0h | Event #20 |
19 | E19 | W | 0h | Event #19 |
18 | E18 | W | 0h | Event #18 |
17 | E17 | W | 0h | Event #17 |
16 | E16 | W | 0h | Event #16 |
15 | E15 | W | 0h | Event #15 |
14 | E14 | W | 0h | Event #14 |
13 | E13 | W | 0h | Event #13 |
12 | E12 | W | 0h | Event #12 |
11 | E11 | W | 0h | Event #11 |
10 | E10 | W | 0h | Event #10 |
9 | E9 | W | 0h | Event #9 |
8 | E8 | W | 0h | Event #8 |
7 | E7 | W | 0h | Event #7 |
6 | E6 | W | 0h | Event #6 |
5 | E5 | W | 0h | Event #5 |
4 | E4 | W | 0h | Event #4 |
3 | E3 | W | 0h | Event #3 |
2 | E2 | W | 0h | Event #2 |
1 | E1 | W | 0h | Event #1 |
0 | E0 | W | 0h | Event #0 |