SPRUJ42 User guide | TI.com

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.4.2.113 TPCC_OPT Register

4.2.113.1 TPCC_OPT Register (Offset = 4000h) [reset = 0h]

Options Parameter

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Table 4-1616 Instance Table

Instance Name	Physical Address
EDMA0	52A0 4000h

Figure 4-790 TPCC_OPT Name Register

31	30	29	28	27	26	25	24
PRIV	RES83			PRIVID
R	R			R
0h	0h			0h
23	22	21	20	19	18	17	16
ITCCHEN	TCCHEN	ITCINTEN	TCINTEN	WIMODE	RES84	TCC
R/W	R/W	R/W	R/W	R/W	R	R/W
0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
TCC				TCCMODE	FWID
R/W				R/W	R/W
0h				0h	0h
7	6	5	4	3	2	1	0
RES85				STATIC	SYNCDIM	DAM	SAM
R				R/W	R/W	R/W	R/W
0h				0h	0h	0h	0h

Table 4-1617 TPCC_OPT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PRIV	R	0h	Privilege level: privilege level [supervisor vs. user] for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege
30:28	RES83	R	0h	RESERVE FIELD
27:24	PRIVID	R	0h	Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus.
23	ITCCHEN	R/W	0h	Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled.
22	TCCHEN	R/W	0h	Transfer complete chaining enable: 0:Transfer complete chaining is disabled. 1:Transfer complete chaining is enabled.
21	ITCINTEN	R/W	0h	Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled [corresponding IER[TCC] bit must be set to 1 to generate interrupt]
20	TCINTEN	R/W	0h	Transfer complete interrupt enable: 0:Transfer complete interrupt is disabled. 1:Transfer complete interrupt is enabled [corresponding IER[TCC] bit must be set to 1 to generate interrupt]
19	WIMODE	R/W	0h	Backward compatibility mode: 0:Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission [0 means 1 1 means 2 ... ] and forces ACNT to be treated as a word-count [left shifted by 2 by hardware to create byte cnt for TR submission]
18	RES84	R	0h	RESERVE FIELD
17:12	TCC	R/W	0h	Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER [bit CER[TCC]] for chaining or in IER [bit IER[TCC]] for interrupts.
11	TCCMODE	R/W	0h	Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0:Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC [which was returned from the peripheral]. 1:Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally .
10:8	FWID	R/W	0h	FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC.
7:4	RES85	R	0h	RESERVE FIELD
3	STATIC	R/W	0h	Static Entry: 0:Entry is updated as normal 1:Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed.
2	SYNCDIM	R/W	0h	Transfer Synchronization Dimension: 0:A-Sync Each event triggers the transfer of ACNT elements. 1:AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements
1	DAM	R/W	0h	Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0:INCR Dst addressing within an array increments. Dst is not a FIFO. 1:FIFO Dst addressing within an array wraps around upon reaching FIFO width.
0	SAM	R/W	0h	Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0:INCR Src addressing within an array increments. Source is not a FIFO. 1:FIFO Src addressing within an array wraps around upon reaching FIFO width.