SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Receive frame watchdog control register.
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Instance Name | Physical Address |
---|---|
FSI_RX0 | 5029 0020h |
FSI_RX1 | 5029 1020h |
FSI_RX2 | 502B 0020h |
FSI_RX3 | 502B 1020h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | FRAME_WD_EN | FRAME_WD_CNT_RST | |||||
R | R/W | R/W | |||||
0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:2 | RESERVED_1 | R | 0h | Reserved |
1 | FRAME_WD_EN | R/W | 0h | Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF] is reached, it will generate a frame watchdog timeout event [RX_EVT_STS.FRAME_WD_TO] and the counter value will reset to 0 and continue counting on the next valid start-of-frame. 0h[R/W] = The frame watchdog counter is disabled and not running. 1h[R/W] = The frame watchdog counter logic is enabled and running. |
0 | FRAME_WD_CNT_RST | R/W | 0h | Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter 0h[R/W] = Clear the FRAME_WD_CNT_RST. 1h[W] = The frame watchdog counter will be reset to 0. |