SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Receive ping watchdog control register.
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Instance Name | Physical Address |
---|---|
FSI_RX0 | 5029 002Ch |
FSI_RX1 | 5029 102Ch |
FSI_RX2 | 502B 002Ch |
FSI_RX3 | 502B 102Ch |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PING_WD_EN | PING_WD_RST | |||||
R | R/W | R/W | |||||
0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:2 | RESERVED_1 | R | 0h | Reserved |
1 | PING_WD_EN | R/W | 0h | Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached, it will generate a ping watchdog timeout event [RX_EVT_STS.PING_WD_TO] and the counter value will reset to 0, and resume counting 0h[R/W] = The ping watchdog counter is disabled and not running. 1h[R/W] = The ping watchdog counter logic is enabled and running. |
0 | PING_WD_RST | R/W | 0h | Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter 0h[R/W] = Clear the PING_WD_RST. 1h[W] = The ping watchdog counter will be reset to 0. |