SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.21.1 FSI_RX_CFG_RX_LOCK_CTRL Register (Offset = 3Ch) [reset = 0h]

Receive lock control register.

Table 3-1034 Instance Table

Figure 3-486 FSI_RX_CFG_RX_LOCK_CTRL Name Register

Table 3-1035 FSI_RX_CFG_RX_LOCK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15:8	KEY	W	0h	Write Key. In order to write to this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after Writing, so it must be written again for every change to this register.
7:1	RESERVED_1	R	0h	Reserved
0	LOCK	R/W	0h	Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked, further writes will not take effect until SYSRS unlocks the register. Once set, further writes even to this bit will be ignored. 0h[R/W] = Receive control registers can be modified and are not locked. 1h[R/W] = Receive control registers are locked and cannot be modified until this bit is cleared by SYSRS. Any further writes to this bit are ignored. Note: The KEY field must contatin 0xA5 for any write to this bit to take effect.