SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.34.1 FSI_RX_CFG_RX_VIS_1 Register (Offset = 70h) [reset = 0h]

Receive debug visibility register 1

Table 3-1060 Instance Table

Figure 3-499 FSI_RX_CFG_RX_VIS_1 Name Register

Table 3-1061 FSI_RX_CFG_RX_VIS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:4	RESERVED_2	R	0h	Reserved
3	RX_CORE_STS	R	0h	Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set, the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has detected and end of frame error or a frame type error. This bit can also be set if the receiver becomes corrupted due to noise on the signal lines. If the receiver has experienced a ping watchdog or frame watchdog timeout, this bit should be read to determine if the cause was due to a corrupt transaction, thus putting the receiver core into an unrecoverable state. Only a soft reset will reset the recevier core and thus reset this bit. 0h[R] The receiver core is operating normally. 1h[R] The receiver core has entered into an error state and should be reset.
2:0	RESERVED_1	R	0h	Reserved