SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Transmit operation control register high.
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Instance Name | Physical Address |
---|---|
FSI_TX0 | 5028 000Ah |
FSI_TX1 | 5028 100Ah |
FSI_TX2 | 502A 000Ah |
FSI_TX3 | 502A 100Ah |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_2 | EXT_TRIG_SEL | ||||||
R | R/W | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXT_TRIG_SEL | ECC_SEL | FORCE_ERR | RESERVED_1 | ||||
R/W | R/W | R/W | R | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | RESERVED_2 | R | 0h | Reserved |
12:7 | EXT_TRIG_SEL | R/W | 0h | External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h[R/W] = Trigger 1 is the source. 01h[R/W] = Trigger 2 is the source. 02h[R/W] = Trigger 3 is the source. ... 3Fh [R/W] = Trigger 64 is the source. |
6 | ECC_SEL | R/W | 0h | ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used. |
5 | FORCE_ERR | R/W | 0h | Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The receiver will treat the data as invalid and can handle this as needed. Note: DO NOT use FORCE_ERR if using the SW CRC mode [FSI Transmit]. 0h[R/W] = The CRC will not be forced to 0. 1h[R/W] = The CRC will be forced to 0 in a buffer overrun or underrun condition. |
4:0 | RESERVED_1 | R | 0h | Reserved |