SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.10.2.17 FSI_TX_CFG_TX_EVT_CLR Register

10.2.17.1 FSI_TX_CFG_TX_EVT_CLR Register (Offset = 2Ch) [reset = 0h]

Transmit event and error clear register.

Table 3-1100 Instance Table

Instance Name	Physical Address
FSI_TX0	5028 002Ch
FSI_TX1	5028 102Ch
FSI_TX2	502A 002Ch
FSI_TX3	502A 102Ch

Figure 3-518 FSI_TX_CFG_TX_EVT_CLR Name Register

15	14	13	12	11	10	9	8
RESERVED_1
R
0h
7	6	5	4	3	2	1	0
RESERVED_1				PING_TRIGGERED	BUF_OVERRUN	BUF_UNDERRUN	FRAME_DONE
R				W	W	W	W
0h				0h	0h	0h	0h

Table 3-1101 FSI_TX_CFG_TX_EVT_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
15:4	RESERVED_1	R	0h	Reserved
3	PING_TRIGGERED	W	0h	Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0. Note: This bit may not always be cleared when Writing to the corresponding TX_EVT_CLR bit. If PING_TIMEOUT MODE is configured to be 0, a hardware ping timeout may occur when another frame is actively being transmitted. In this case, if this bit still shows as 1 after the clear bit is written then the ping frame has been triggered but not serviced. This bit does not indicate that the ping frame has been completely sent, only that it has been triggered by the timeout event.
2	BUF_OVERRUN	W	0h	Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0.
1	BUF_UNDERRUN	W	0h	Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0.
0	FRAME_DONE	W	0h	Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h[W] = Writing a 0 to this bit will have no effect. 1h[W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0.