SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

10.2.22.1 FSI_TX_CFG_TX_DLYLINE_CTRL Register (Offset = 48h) [reset = 0h]

Transmit delay Line control register.

Table 3-1110 Instance Table

Figure 3-523 FSI_TX_CFG_TX_DLYLINE_CTRL Name Register

Table 3-1111 FSI_TX_CFG_TX_DLYLINE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED_1	R	0h	Reserved
14:10	TXD1_DLY	R/W	0h	Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD1 path. TXD1 is taken directly from the pin. 1h[R/W] One delay element is included in the TXD1 path. 2h[R/W] Two delay elements are included in the TXD1 path. ... 1Fh [R/W] 31 delay elements are included in the TXD1 path, the maximum.
9:5	TXD0_DLY	R/W	0h	Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXD0 path. TXD0 is taken directly from the pin. 1h[R/W] One delay element is included in the TXD0 path. 2h[R/W] Two delay elements are included in the TXD0 path. ... 1Fh [R/W] 31 delay elements are included in the TXD0 path, the maximum.
4:0	TXCLK_DLY	R/W	0h	Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h[R/W] Zero delay elements are included in the TXCLK path. TXCLK is taken directly from the pin. 1h[R/W] One delay element is included in the TXCLK path. 2h[R/W] Two delay elements are included in the TXCLK path. ... 1Fh [R/W] 31 delay elements are included in the TXCLK path, the maximum.