SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.2.92.1 IOMUX_PR0_PRU0_GPO6_CFG_REG Register (Offset = 16Ch) [reset = 5F7h]

Table 2-1253 Instance Table

Instance Name	Physical Address
MSS_IOMUX	5310 016Ch

Figure 2-625 IOMUX_PR0_PRU0_GPO6_CFG_REG Name Register

Table 2-1254 IOMUX_PR0_PRU0_GPO6_CFG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
29:21	RESERVED	NONE	0h	Reserved
20	INP_INV_SEL	R/W	0h	Select Value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted
19:18	QUAL_SEL	R/W	0h	Select Value for chosing input qualifer type for PAD. 00 : Sync, 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async
17:16	GPIO_SEL	R/W	0h	R5F CPU ownership select for GPIO. 0 : GPO0, 1 :GPO1, 2 : GPO2, 3:GPO3
15:11	RESERVED	NONE	0h	Reserved
10	SC1	R/W	1h	IO Slew Rate Control : 0 : higher slew rate. 1:Lower slew rate.
9	PUPDSEL	R/W	0h	Internal Pull Resistor Direction Control bit 0:Pull-down Resistor 1:Pull-up Resistor
8	PI	R/W	1h	Pull Inhibit/Pull Disable 0 -- Enable 1- Disable
7	OE_OVERRIDE	R/W	1h	Active Low Output Override
6	OE_OVERRIDE_CTRL	R/W	1h	Output Override Control bit (Active Low) This bit provides a software override for the default OE_N/GZ hardware control. 0:Enable pad input override 1:Disable pad input override
5	IE_OVERRIDE	R/W	1h	Input Override (Active Low) 0:Override pad input signal to 0 (LOW) 1:Override pad input signal to 1 (HIGH)
4	IE_OVERRIDE_CTRL	R/W	1h	Input Override (Active Low) 0:Override pad input signal to 0 (LOW) 1:Override pad input signal to 1 (HIGH) Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware
3:0	FUNC_SEL	R/W	7h	Function select