SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer.
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Instance Name | Physical Address |
---|---|
MCRC0 | 3500 008Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED1 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CRC_WDTOPLD2 | |||||||
R/W | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CRC_WDTOPLD2 | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_WDTOPLD2 | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | RESERVED1 | R | 0h | |
23:0 | CRC_WDTOPLD2 | R/W | 0h | Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns. |