SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.1 MMC_HL_HWINFO Register

15.2.1.1 MMC_HL_HWINFO Register (Offset = 4h) [reset = 8h]

Information about the IP module's hardware configuration, i.e. typically the module's HDL generics (if any).
Actual field format and encoding is up to the module's designer to decide.

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Table 5-1764 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0004h

Figure 5-870 MMC_HL_HWINFO Name Register

31	30	29	28	27	26	25	24
RESERVED
R
0h
23	22	21	20	19	18	17	16
RESERVED
R
0h
15	14	13	12	11	10	9	8
RESERVED
R
0h
7	6	5	4	3	2	1	0
RESERVED	RETMODE	MEM_SIZE				MERGE_MEM	MADMA_EN
R	R	R				R	R
0h	0h	2h				0h	0h

Table 5-1765 MMC_HL_HWINFO Register Field Descriptions

Bit	Field	Type	Reset	Description
31:7	RESERVED	R	0h
6	RETMODE	R	0h	Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 1 Retention mode enabled 0 Retention mode disabled
5:2	MEM_SIZE	R	2h	Memory size for FIFO buffer: 8 Memory of 4096 bytes, max block length is 2048 bytes 4 Memory of 2048 bytes, max block length is 2048 bytes 2 Memory of 1024 bytes, max block length is 1024 bytes 1 Memory of 512 bytes, max block length is 512 bytes
1	MERGE_MEM	R	0h	Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing. 1 A single memory is used with multiplexed addresses, data and clocks. 0 2 memories instantiated, one per data transfer direction.
0	MADMA_EN	R	0h	Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA. 1 Controller supports ADMA 0 No Master DMA (ADMA) management supported