SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.8 MMC_DLL Register

15.2.8.1 MMC_DLL Register (Offset = 134h) [reset = 80000000h]

DLL control and status register

This register is used for tuning procedure required for SDR104 speed mode.
It gives visibility and control on the DLL.

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Table 5-1778 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0134h

Figure 5-877 MMC_DLL Name Register

31	30	29	28	27	26	25	24
DLL_SOFT_RESET	LOCK_TIMER	MAX_LOCK_DIFF
R/W	R/W	R/W
1h	0h	0h
23	22	21	20	19	18	17	16
MAX_LOCK_DIFF		FORCE_SR_F		FORCE_SR_C
R/W		R/W		R/W
0h		0h		0h
15	14	13	12	11	10	9	8
FORCE_SR_C			FORCE_VALUE	SLAVE_RATIO
R/W			R/W	R/W
0h			0h	0h
7	6	5	4	3	2	1	0
SLAVE_RATIO		RESERVED		DLL_UNLOCK_CLEAR	DLL_UNLOCK_STICKY	DLL_CALIB	DLL_LOCK
R/W		R		R/W	R	R/W	R
0h		0h		0h	0h	0h	0h

Table 5-1779 MMC_DLL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DLL_SOFT_RESET	R/W	1h	Soft reset for DLL, active HIGH. 1 Reset is in progress 1 Issue soft reset 0 Reset completed. 0 No action.
30	LOCK_TIMER	R/W	0h	Timer for the dll_lock signal to be asserted after reset. 1 66560 cycles 0 1024 cycles (equivalent to DLL fast mode lock)
29:22	MAX_LOCK_DIFF	R/W	0h	Maximum number of taps that the master DLLs clock period measurement can deviate without resulting in the master DLL losing lock.
21:20	FORCE_SR_F	R/W	0h	Forced fine delay value.
19:13	FORCE_SR_C	R/W	0h	Forced coarse delay value
12	FORCE_VALUE	R/W	0h	Put forced values to target DLL, ignoring master DLL output and ratio value. 1 Put force value. 0 Do not put force value
11:6	SLAVE_RATIO	R/W	0h	Fraction of a clock cycle for the shift to be implemented, in units of 256ths of a clock cycle. 63 4 clocks delay 16 Full clock delay 14 315 degrees delay 12 270 degrees delay 10 225 degrees delay 8 180 degrees delay 6 135 degrees delay 4 90 degrees delay 2 45 degrees delay 0 0 degree delay
5:4	RESERVED	R	0h
3	DLL_UNLOCK_CLEAR	R/W	0h	Clears the phy_reg_status_mdll_unlock_sticky flags of the DLL. 1 Clears the flag. 0 No effect.
2	DLL_UNLOCK_STICKY	R	0h	Asserted when any single period measurement exceeds MAX_LOCK_DIFF.
1	DLL_CALIB	R/W	0h	Enables Target DLL to update new delay values. 1 Enabled 0 Disabled
0	DLL_LOCK	R	0h	Master DLL lock status. 1 DLL is locked 0 DLL is not locked