SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.9 MMC_SDMASA Register

15.2.9.1 MMC_SDMASA Register (Offset = 200h) [reset = 0h]

SDMA System Address / Argument 2 Register.

Table 5-1780 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0200h

Figure 5-878 MMC_SDMASA Name Register

31	30	29	28	27	26	25	24
SDMA_ARG2
R/W
0h
23	22	21	20	19	18	17	16
SDMA_ARG2
R/W
0h
15	14	13	12	11	10	9	8
SDMA_ARG2
R/W
0h
7	6	5	4	3	2	1	0
SDMA_ARG2
R/W
0h

Table 5-1781 MMC_SDMASA Register Field Descriptions

Bit	Field	Type	Reset	Description
31:0	SDMA_ARG2	R/W	0h	SDMA System Address / Argument 2 This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. [1] SDMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing [i.e., after a transaction has stopped]. Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register 003h is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register. [2] Argument 2 This register is used with the Auto CMD23 to set a 32-bit block count value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used without AMDA, the available block count value is limited by the Block Count register. 65535 blocks is the maximum value in this case.