SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.12 MMC_CMD Register

15.2.12.1 MMC_CMD Register (Offset = 20Ch) [reset = 0h]

Command and Transfer Mode Register

MMCHS_CMD[31:16] = the command register
MMCHS_CMD[15:0] = the transfer mode.

This register configures the data and command transfers. A write into the most significant byte send the command. A write into MMCHS_CMD[15:0] registers during data transfer has no effect.

This register shall be used for any card.

Note: In SYSTEST mode, a write into MMCHS_CMD register will not start a transfer.

Return to Summary Table

Table 5-1786 Instance Table

Instance Name	Physical Address
MMCSD0	4830 020Ch

Figure 5-881 MMC_CMD Name Register

31	30	29	28	27	26	25	24
RESERVED2		INDX
R		R/W
0h		0h
23	22	21	20	19	18	17	16
CMD_TYPE		DP	CICE	CCCE	RESERVED1	RSP_TYPE
R/W		R/W	R/W	R/W	R	R/W
0h		0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
RESERVED
R
0h
7	6	5	4	3	2	1	0
RESERVED		MSBS	DDIR	ACEN		BCE	DE
R		R/W	R/W	R/W		R/W	R/W
0h		0h	0h	0h		0h	0h

Table 5-1787 MMC_CMD Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED2	R	0h
29:24	INDX	R/W	0h	Command index Binary encoded value from 0 to 63 specifying the command number send to card 63 CMD63 or ACMD63 62 CMD62 or ACMD62 61 CMD61 or ACMD61 60 CMD60 or ACMD60 59 CMD59 or ACMD59 58 CMD58 or ACMD58 57 CMD57 or ACMD57 56 CMD56 or ACMD56 55 CMD55 or ACMD55 54 CMD54 or ACMD54 53 CMD53 or ACMD53 52 CMD52 or ACMD52 51 CMD51 or ACMD51 50 CMD50 or ACMD50 49 CMD49 or ACMD49 48 CMD48 or ACMD48 47 CMD47 or ACMD47 46 CMD46 or ACMD46 45 CMD45 or ACMD45 44 CMD44 or ACMD44 43 CMD43 or ACMD43 42 CMD42 or ACMD42 41 CMD41 or ACMD41 40 CMD40 or ACMD40 39 CMD39 or ACMD39 38 CMD38 or ACMD38 37 CMD37 or ACMD37 36 CMD36 or ACMD36 35 CMD35 or ACMD35 34 CMD34 or ACMD34 33 CMD33 or ACMD33 32 CMD32 or ACMD32 31 CMD31 or ACMD31 30 CMD30 or ACMD30 29 CMD29 or ACMD29 28 CMD28 or ACMD28 27 CMD27 or ACMD27 26 CMD26 or ACMD26 25 CMD25 or ACMD25 24 CMD24 or ACMD24 23 CMD23 or ACMD23 22 CMD22 or ACMD22 21 CMD21 or ACMD21 20 CMD20 or ACMD20 19 CMD19 or ACMD19 18 CMD18 or ACMD18 17 CMD17 or ACMD17 16 CMD16 or ACMD16 15 CMD15 or ACMD15 14 CMD14 or ACMD14 13 CMD13 or ACMD13 12 CMD12 or ACMD12 11 CMD11 or ACMD11 10 CMD10 or ACMD10 9 CMD9 or ACMD9 8 CMD8 or ACMD8 7 CMD7 or ACMD7 6 CMD6 or ACMD6 5 CMD5 or ACMD5 4 CMD4 or ACMD4 3 CMD3 or ACMD3 2 CMD2 or ACMD2 1 CMD1 or ACMD1 0 CMD0 or ACMD0
23:22	CMD_TYPE	R/W	0h	Command type This register specifies three types of special command: Suspend, Resume and Abort. These bits shall be set to 00bfor all other commands. 3 Abort command CMD12, CMD52 for writing " I/O Abort" in CCCR 2 CMD52 for writing "Function Select" in CCCR 1 CMD52 for writing "Bus Suspend" in CCCR 0 Others Commands
21	DP	R/W	0h	Data present select This register indicates that data is present and DAT line shall be used. It must be set to 0 in the following conditions: - command using only CMD line - command with no data transfer but using busy signal on DAT[0] - Resume command 1 Command with data transfer 0 Command with no data transfer
20	CICE	R/W	0h	Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it is reported as a command index error [MMCSD_STAT[CIE] set to1] Note: The register CICE cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued. 1 Index check enable 0 Index check disable
19	CCCE	R/W	0h	Command CRC check enable This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC error [MMCSD_STAT[CCRC] set to 1]. Note: The register CCCE cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued. 1 CRC7 check enable 0 CRC7 check disable
18	RESERVED1	R	0h
17:16	RSP_TYPE	R/W	0h	Response type This bits defines the response type of the command 3 Response Length 48 bits with busy after response 2 Response Length 48 bits 1 Response Length 136 bits 0 No response
15:6	RESERVED	R	0h
5	MSBS	R/W	0h	Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit shall be set to 0. 1 Multi block. When Block Count is disabled (MMCHS_CMD[BCE] is set to 0) in Multiple block transfers (MMCHS_CMD[MSBS] is set to 1), the module can perform infinite transfer. 0 Single block. If this bit is 0, it is not necessary to set the register MMCHS_BLK[NBLK].
4	DDIR	R/W	0h	Data transfer Direction Select This bit defines either data transfer will be a read or a write. 1 Data Read (card to host) 0 Data Write (host to card)
3:2	ACEN	R/W	0h	Auto CMD Enable - SD card only. This field determines use of auto command functions. There are two methods to stop Multiple-block read and write operation [1] Auto CMD12 Enable When this field is set to 01b the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the Auto CMD Error Status register. The Host Driver shall not set this bit if the command does not require CMD12. In particular, secure commands defined in the Part 3 File Security specification do not require CMD12. [2] Auto CMD23 Enable When this bit field is set to 10b the Host Controller issues a CMD23 automatically before issuing a command specified in the Command Register. The Host Controller Version 3.00 and later shall support this function. The following conditions are required to use the Auto CMD23. Auto CMD23 Supported [Host Controller Version is 3.00 or later] A memory card that supports CMD23 [SCR[33]=1] If DMA is used, it shall be ADMA. Only when CMD18 or CMD25 is issued [Note, the Host Controller does not check command index.] Auto CMD23 can be used with or without ADMA. By Writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Command register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register. 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register. 3 Reserved 2 Auto CMD23 Enable 1 Auto CMD12 enable or CCS detection enabled. 0 Auto Command Disabled
1	BCE	R/W	0h	Block Count Enable Multiple block transfers only. This bit is used to enable the block count register [MMCSD_BLK[NBLK]]. When Block Count is disabled [MMCSD_CMD[BCE] is set to 0] in Multiple block transfers [MMCSD_CMD[MSBS] is set to 1], the module can perform infinite transfer. 1 Block count enabled for multiple block transfer with known number of blocks 0 Block count disabled for infinite transfer.
0	DE	R/W	0h	DMA Enable This bit is used to enable DMA mode for host data access. 1 DMA mode enable 0 DMA mode disable