SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.17 MMC_DATA Register

15.2.17.1 MMC_DATA Register (Offset = 220h) [reset = 0h]

Data Register

This register is the 32-bit entry point of the buffer for read or write data transfers.

The buffer size is 32bits x256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput.

Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer.

Example 1: Byte or 16-bit access

Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK
Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK
Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad .

Return to Summary Table

Table 5-1796 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0220h

Figure 5-886 MMC_DATA Name Register

31	30	29	28	27	26	25	24
DATA
R/W
0h
23	22	21	20	19	18	17	16
DATA
R/W
0h
15	14	13	12	11	10	9	8
DATA
R/W
0h
7	6	5	4	3	2	1	0
DATA
R/W
0h

Table 5-1797 MMC_DATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31:0	DATA	R/W	0h	Data Register [31:0] In functional mode [MMCSD_CON[MODE] set to the default value 0] , A read access to this register is allowed only when the buffer read enable status is set to 1 [MMCSD_PSTATE[BRE]], otherwise a bad access [MMCSD_STAT[BADA]] is signaled. A write access to this register is allowed only when the buffer write enable status is set to 1[MMCSD_STATE[BWE]], otherwise a bad access [MMCSD_STAT[BADA]] is signaled and the data is not written.