SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Present State Register
The Host can get status of the Host Controller from this 32-bit read only register.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 4830 0224h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED2 | CLEV | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DLEV | WP | CDPL | CSS | CINS | |||
| R | R | R | R | R | |||
| 0h | 0h | 1h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | BRE | BWE | RTA | WTA | |||
| R | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RTR | DLA | DATI | CMDI | |||
| R | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED2 | R | 0h | |
| 24 | CLEV | R | 0h | CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time. 1 The CMD line level is 1. 0 The CMD line level is 0. |
| 23:20 | DLEV | R | 0h | DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. The value of these registers after reset depends on the DAT lines level at that time. |
| 19 | WP | R | 0h | Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin [SDWP] level. The value of this register after reset depends on the protect input pin [SDWP] level at that time. 1 If MMCHS_CON[WPP] is set to 0 (default),
the card is not write protected, otherwise
the card is protected.
0 If MMCHS_CON[WPP] is set to 0 (default),
the card is write protected, otherwise the
card is not protected. |
| 18 | CDPL | R | 1h | Card detect pin level This bit reflects the inverse value of the card detect input pin [SDCD], debouncing is not performed on this bit and bit is valid only when Card State Stable [MMCSD_PSTAE[CSS]] is set to 1. Use of this bit is limited to testing since it must be debounced y software. The value of this register after reset depends on the card detect input pin [SDCD] level at that time. 1 The value of the card detect input pin
(SDCD) is 0
0 The value of the card detect input pin
(SDCD) is 1 |
| 17 | CSS | R | 0h | Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable [MMCSD_PSTATE[CDPL]]. Debouncing is performed on the card detect input pin [SDCD] to detect card stability. This bit is not affected by a software reset. 1 No card or card inserted 0 Reset or Debouncing |
| 16 | CINS | R | 0h | Card inserted This bit is the debounced value of the card detect input pin [SDCD]. An inactive to active transition of the card detect input pin [SDCD] will generate a card insertion interrupt [MMCSD_STAT[CINS]]. A active to inactive transition of the card detect input pin [SDCD] will generate a card removal interrupt [MMCSD_STAT[REM]]. This bit is not affected by a software reset. 1 If MMCHS_CON[CDP] is set to 1, the card
has been inserted from the card slot. If
MMCHS_CON[CDP] is set to 0 no card is
detected. The card may have been removed
from the card slot.
0 If MMCHS_CON[CDP] is set to 1, no card is
detected. The card may have been removed
from the card slot. If MMCHS_CON[CDP] is
set to 0, the card has been inserted. |
| 15:12 | RESERVED1 | R | 0h | |
| 11 | BRE | R | 0h | Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCSD_BLK[BLEN] has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt [MMCSD_STAT[BRR]]. 1 Read BLEN bytes enable. Readable data
exists in the buffer.
0 Read BLEN bytes disable |
| 10 | BWE | R | 0h | Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data. 1 There is enough space in the buffer to
write BLEN bytes of data.
0 There is no room left in the buffer to
write BLEN bytes of data. |
| 9 | RTA | R | 0h | Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request [MMCSD_HCTL[CR]] following a stop at block gap request. This bit is set to 0 when all data have been read by the local host after last block or after a stop at block gap request. 1 read data transfer on going. 0 No valid data on the DAT lines. |
| 8 | WTA | R | 0h | Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request [MMCSD_HCTL[CR]] following a stop at block gap request. This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request. 1 Write data transfer on going. 0 No valid data on the DAT lines. |
| 7:4 | RESERVED | R | 0h | |
| 3 | RTR | R | 0h | Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting Execute Tuning in the Host Control 2 register. Changing of this bit from 0 to 1 generates Re-Tuning Event. Refer to Normal Interrupt Status registers for more detail. This bit isn't set to 1 if Sampling Clock Select in the Host Control 2 register is set to 0 [using fixed sampling clock]. Refer to Re-Tuning Modes in the Capabilities register for more detail. 1 Sampling clock needs re-tuning 0 Fixed or well tuned sampling clock |
| 2 | DLA | R | 0h | DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions [card to host]: This bit is set to 1 after the end bit of read command or by activating continue request MMCSD_HCTL[CR]. This bit is set to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions [host to card]: This bit is set to 1 after the end bit of write command or by activating continue request MMCSD_HCTL[CR]. This bit is set to 0 on the end of busy event for the last block; host controller must wait 8 clock cycles with line not busy to really consider not "busy state" or after the busy block as a result of a stop at gap request. 1 DAT Line active 0 DAT Line inactive |
| 1 | DATI | R | 0h | Command inhibit[DAT] This status bit is generated if either DAT line is active [MMCSD_PSTATE[DLA]] or Read transfer is active [MMCSD_PSTATE[RTA]] or when a command with busy is issued. This bit prevents the local host to issue a command. A change of this bit from 1 to 0 generates a transfer complete interrupt [MMCSD_STAT[TC]]. 1 Issuing of command using DAT lines is not
allowed
0 Issuing of command using the DAT lines is
allowed |
| 0 | CMDI | R | 0h | Command inhibit[CMD] This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0 in either the following cases: - After the end bit of the command response, excepted if there is a command conflict error [MMCSD_STAT[CCRC] or MMCSD_STAT[CEB] set to 1] or a Auto CMD12 is not executed [MMCSD_AC12[ACNE]]. - After the end bit of the command without response [MMCSD_CMD[RSP_TYPE] set to "00"] In case of a command data error is detected [MMCSD_STAT[CTO] set to 1], this register is not automatically cleared. 1 Issuing of command using CMD line is not
allowed
0 Issuing of command using CMD line is
allowed |