SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Host Control Register
This register defines the host controls to set power, wakeup and transfer parameters.
MMCHS_HCTL[31:24] = Wakeup control
MMCHS_HCTL[23:16] = Block gap control
MMCHS_HCTL[15:8] = Power control
MMCHS_HCTL[7:0] = Host control.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 4830 0228h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED3 | OBWE | REM | INS | IWE | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED2 | IBG | RWC | CR | SBGR | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | SDVS | SDBP | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CDSS | CDTL | RESERVED | DMAS | HSPE | DTW | LED | |
| R/W | R/W | R | R/W | R/W | R/W | R | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED3 | R | 0h | |
| 27 | OBWE | R/W | 0h | Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled [MMCSD_SYSCONFIG[ENAWAKEUP]]. The write to this register is ignored when MMCSD_CON[OBIE] is not set. 1 Enable wakeup on 'Out-of-Band' Interrupt 0 Disable wakeup on 'Out-of-Band' Interrupt |
| 26 | REM | R/W | 0h | Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled [MMCSD_SYSCONFIG[ENAWAKEUP]]. 1 Enable wakeup on card removal 0 Disable wakeup on card removal |
| 25 | INS | R/W | 0h | Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled [MMCSD_SYSCONFIG[ENAWAKEUP]]. 1 Enable wakeup on card insertion 0 Disable wakeup on card insertion |
| 24 | IWE | R/W | 0h | Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled [MMCSD_SYSCONFIG[ENAWAKEUP]]. 1 Enable wakeup on card interrupt 0 Disable wakeup on card interrupt |
| 23:20 | RESERVED2 | R | 0h | |
| 19 | IBG | R/W | 0h | Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be set to 0. 1 Enable interrupt detection at the block gap
in 4-bit mode
0 Disable interrupt detection at the block
gap in 4-bit mode |
| 18 | RWC | R/W | 0h | Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap [MMCSD_HCTL[SBGR]] generates a read wait period after the current end of block. Be careful, if read wait is not supported it may cause a conflict on DAT line. 1 Enable Read Wait Control
0 Disable Read Wait Control. Suspend/Resume
cannot be supported. |
| 17 | CR | R/W | 0h | Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap [MMCSD_HCTL[SBGR]]. Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when transfer has restarted i.e DAT line is active [MMCSD_PSTATE[DLA]] or transferring data [MMCSD_PSTATE[WTA]]. The Stop at block gap request must be disabled [MMCSD_HCTL[SBGR]=0] before setting this bit. 1 transfer restart 0 No affect |
| 16 | SBGR | R/W | 0h | Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request [MMHS_HCTL[CR]] or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver shall set this bit after all block data written. Until the transfer completion [MMCSD_STAT[TC] set to 1], the host driver shall leave this bit set to 1. If this bit is set, the local host shall not write to the data register [MMCSD_DATA]. 1 Stop at block gap 0 Transfer mode |
| 15:12 | RESERVED1 | R | 0h | |
| 11:9 | SDVS | R/W | 0h | SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system [MMCSD_CAPA[VS18,VS30,VS33]] before starting a transfer. 7 3.3V (Typical) 6 3.0V (Typical) 5 1.8V (Typical) |
| 8 | SDBP | R/W | 0h | SD bus power Before setting this bit, the host driver shall select the SD bus voltage [MMCSD_HCTL[SDVS]]. If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in the command register [MMCSD_CMD] will not start the transfer. A write to this bit has no effect if the selected SD bus voltage MMCSD_HCTL[SDVS] is not supported according to capability register [MMCSD_CAPA[VS*]]. 1 Power on 0 Power off |
| 7 | CDSS | R/W | 0h | Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupt being caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period of debouncing. 1 The Card Detect Test Level is selected (for
test purpose)
0 SDCD# is selected (for normal use) |
| 6 | CDTL | R/W | 0h | Card Detect Test Level: This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. 1 Card Inserted 0 No Card |
| 5 | RESERVED | R | 0h | |
| 4:3 | DMAS | R/W | 0h | DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only meaningful when MADMA_EN is set to 1. When MADMA_EN is set to 0 the bit field is read only and returned value is 0. 3 Reserved 2 32-bit Address ADMA2 is selected 1 Reserved 0 Reserved |
| 2 | HSPE | R/W | 0h | High Speed Enable: Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 [default], the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock. If this bit is set to 1, the Host Controller outputs CMD line and DAT lines at the rising edge of the SD Clock.This bit shall not be set when dual data rate mode is activated in MMCSD_CON[DDR]. 1 High speed mode 0 Normal speed mode |
| 1 | DTW | R/W | 0h | Data transfer width For MMC card, this bit must be set following a valid SWITCH command [CMD6] with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register [CSD and EXT_CSD] must be verified for compliance with MMC standard specification 4.x [see section 3.6]. This register has no effect when the MMC 8-bit mode is selected [register MMCSD_CON[DW8] set to1 ], For SD/SDIO cards, this bit must be set following a valid SET_BUS_WIDTH command [ACMD6] with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register [SCR] must be verified for the supported bus width by the SD card. 1 4-bit Data width (DAT[3:0] used) 0 1-bit Data width (DAT[0] used) |
| 0 | LED | R | 0h | Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored. |