SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.20 MMC_SYSCTL Register

15.2.20.1 MMC_SYSCTL Register (Offset = 22Ch) [reset = 0h]

SD System Control Register

This register defines the system controls to set software resets, clock frequency management and data timeout.

MMCHS_SYSCTL[31:24] = Software resets
MMCHS_SYSCTL[23:16] = Timeout control
MMCHS_SYSCTL[15:0] = Clock control.

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Table 5-1802 Instance Table

Instance Name	Physical Address
MMCSD0	4830 022Ch

Figure 5-889 MMC_SYSCTL Name Register

31	30	29	28	27	26	25	24
RESERVED2					SRD	SRC	SRA
R					R/W	R/W	R/W
0h					0h	0h	0h
23	22	21	20	19	18	17	16
RESERVED1				DTO
R				R/W
0h				0h
15	14	13	12	11	10	9	8
CLKD
R/W
0h
7	6	5	4	3	2	1	0
CLKD		CGS	RESERVED		CEN	ICS	ICE
R/W		R	R		R/W	R	R/W
0h		0h	0h		0h	0h	0h

Table 5-1803 MMC_SYSCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:27	RESERVED2	R	0h
26	SRD	R/W	0h	Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed. DAT finite state machine in both clock domain are also reset. Here below are the registers cleared by MMCSD_SYSCTL[SRD]: - MMCSD_DATA - MMCSD_PSTATE: BRE, BWE, RTA, WTA, DLA and DATI - MMCSD_HCTL: SBGR and CR - MMCSD_STAT: BRR, BWR, BGE and TC OCP and MMC buffer data management is reinitialized. 1 Software reset for DAT line 0 Reset completed
25	SRC	R/W	0h	Software reset for CMD line This bit is set to 1 for reset and released to 0 when completed. CMD finite state machine in both clock domain are also reset. Here below the registers cleared by MMCSD_SYSCTL[SRC]: - MMCSD_PSTATE: CMDI - MMCSD_STAT: CC OCP and MMC command status management is reinitialized. 1 Software reset for CMD line 0 Reset completed
24	SRA	R/W	0h	Software reset for all This bit is set to 1 for reset , and released to 0 when completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers. 1 Software reset for all the design 0 Reset completed
23:20	RESERVED1	R	0h
19:16	DTO	R/W	0h	Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bitfield based on - the maximum read access time [NAC] [Refer to the SD Specification Part1 Physical Layer], - the data read access time values [TAAC and NSAC] in the card specific data register [CSD] of the card, - the timeout clock base frequency [MMCSD_CAPA[TCF]]. If the card does not respond within the specified number of cycles, a data timeout error occurs [MMCSD_STA[DTO]]. The MMCSD_SYSCTL[DTO] register is also used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write. 15 Reserved 14 TCF x 2^27 1 TCF x 2^14 0 TCF x 2^13
15:6	CLKD	R/W	0h	Clock frequency select These bits define the ratio between a reference clock frequency [system dependant] and the output clock frequency on the CLK pin of either the memory card [MMC, SD or SDIO]. 1023 Clock Ref / 1023 3 Clock Ref / 3 2 Clock Ref / 2 1 Clock Ref bypass 0 Clock Ref bypass
5	CGS	R	0h	Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit. This bit is used to select the clock generator mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported [non-zero value is set to Clock Multiplier in the Capabilities register], this bit attribute is RW, and if not supported, this bit attribute is RO and zero is read. This bit depends on the setting of Preset Value Enable in the Host Control 2 register. If the Preset Value Enable = 0, this bit is set by Host Driver. If the Preset Value Enable = 1, this bit is automatically set to a value specified in one of Preset Value registers.
4:3	RESERVED	R	0h
2	CEN	R/W	0h	Clock enable This bit controls if the clock is provided to the card or not. 1 The clock is provided to the card and can be automatically gated when MMCHS_SYSCONFIG[AUTOIDLE] is set to 1 (default value) . The host driver shall wait to set this bit to 1 until the Internal clock is stable (MMCHS_SYSCTL[ICS]). 0 The clock is not provided to the card . Clock frequency can be changed .
1	ICS	R	0h	Internal clock stable [status] This bit indicates either the internal clock is stable or not. 1 The internal clock is stable after enabling the clock (MMCHS_SYSCTL[ICE]) or after changing the clock ratio (MMCHS_SYSCTL[CLKD]). 0 The internal clock is not stable.
0	ICE	R/W	0h	Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock [used for wakeup events] and the OCP clock [used for reads and writes to the module register map] are not affected by this register. 1 The internal clock oscillates and can be automatically gated when MMCHS_SYSCONFIG[AUTOIDLE] is set to 1 (default value) . 0 The internal clock is stopped (very low power state).